1. Technical Field
This disclosure relates to a semiconductor apparatus, and is more particularly, to a stacked semiconductor memory apparatus.
2. Related Art
A three-dimensional arrangement structure having a plurality of memory chips stacked therein is used to improve the degree of integration of a semiconductor memory. A semiconductor memory apparatus using the three-dimensional arrangement structure may be referred to as a stacked semiconductor memory apparatus.
In the stacked semiconductor memory apparatus, each memory chip can be called a slice, and slices may be differently coupled to one another depending on the stacking mechanisms of the stacked semiconductor memory apparatus. Stacking mechanisms of the stacked semiconductor memory apparatus may include a system in package (SIP) method, a package on package (POP) method, a through-silicon via (TSV) method and the like. According to the stacking mechanisms, the slices may be electrically connected to one another using balls, wires or bumps. The TSV method has been proposed as stack method solution for overcoming the reduction in a transmission speed due to the distance to a controller, weakness of a data bandwidth, and the deterioration of data transmission characteristics due to various variables on a package.
FIG. 1 is a schematic diagram of a stacked semiconductor memory apparatus using a typical TSV method. The stacked semiconductor memory apparatus illustrated in FIG. 1 has a configuration in which a master chip Master controls a plurality of is slave chips Slave. The typical stacked semiconductor memory apparatus illustrated in FIG. 1 operates as follows.
When a read or write command is generated from the master chip of the stacked semiconductor memory apparatus, the master chip transmits a first timing signal AYP to the plurality of slave chips Slave. The first timing signal AYP may serve as a source signal of various timing signals generated for a read or write operation by the plurality of slave chips Slave. The first timing signal AYP may also individually exist in each of the plurality of slave chips Slave, and one first timing signal AYP may also be shared by the plurality of slave chips Slave through a single path (such as a TSV in the TSV method). The number of TSVs in the contemporary stacked semiconductor memory apparatus using the TSV method has been gradually reduced from the consideration of a layout and an available area so that the first timing signal AYP illustrated in FIG. 1 may be formed of a single signal transmitted through a single path (for example, a TSV) shared by the plurality of slave chips Slave.
After the first timing signal AYP is received, the plurality of slave chips Slave generate various timing signals for a read or write operation through respective timing signal generation units 100. The various timing signals will be described later with reference to FIG. 2. Each of the plurality of slave chips Slave generates second timing signals PIN for a read operation. The second timing signal PIN includes synchronization information required when the plurality of slave chips Slave transmit data to the master chip. The master chip is receives the data, which is transmitted from the plurality of slave chips Slave, in synchronization with the second timing signal PIN. In the stacked semiconductor memory apparatus illustrated in FIG. 1, the plurality of slave chips Slave may share a single path for the second timing signals PIN transmitted to the master chip. Furthermore, the plurality of slave chips Slave may share a single path for the data transmitted to the master chip. Accordingly, the second timing signal PIN should be activated at an accurate timing. In more detail, since the plurality of slave chips Slave and the master chip share a path for data being transmitted and a path for the second timing signal PIN being transmitted, it is necessary for each slave chip Slave to accurately transmit the data and the second timing signal PIN within the time for using the path. Here, skew for the second timing signal PIN may be problematic. Each slave chip Slave generates the second timing signal PIN after a predetermined time passes from the point of time at which the first timing signal AYP is triggered. However, the second timing signal PIN generated by each slave chip Slave may be deviated from a target point of time due to PVT (process, voltage, temperature) variation. Moreover, since each slave chip Slave may be fabricated from different wafers rather than the same wafer, the second timing signal PIN is significantly affected by process variation. Such skew of the second timing signal PIN reduces a timing margin, resulting in the reduction in effective data area such as data eye.
One problem with typical stacked semiconductor apparatus is deterioration of operation due to skew. As well as the second timing signal PIN, skew for internal signals of each slave chip Slave deteriorates the operation characteristics of a stacked semiconductor memory apparatus. Furthermore, timing margins of various internal signals have been gradually reduced with the high speed operation of a semiconductor memory apparatus. In this regard, there has been increasing demand for a stacked semiconductor memory apparatus capable of correcting the skew for internal signals of each slave chip Slave.
FIG. 2 is a detailed block diagram of the typical timing signal generation unit 100 illustrated in FIG. 1.
As mentioned above, the timing signal generation unit 100 included in each slave chip Slave generates internal timing signals required for read and write operations thereof. The internal timing signals may include a first application signal YI, a second application signal BWEN, a third application signal IOSTBP, and a second timing signal PIN. The first application signal YI is used to control an electrical connection between segment input/output lines and bit lines and bit bar lines in a read or write operation. The second application signal BWEN is used to control an electrical connection between input/output lines different from each other in a write operation. The third application signal IOSTBP is used to control an electrical connection between lines different from each other in a read operation. The second timing signal PIN is outputted from the final terminal of the timing signal generation unit 100 and includes the synchronization information required when the plurality of slave chips Slave transmit data to the master chip as mentioned above. The timing signal generation unit 100 includes a plurality of delay circuits 110, 120, 130 and 140. If the first timing signal AYP is received, output units of the plurality of delay circuits 110, 120, 130 and 140 output the first application signal YI, the second application signal BWEN, the third application signal IOSTBP, and the second timing signal PIN, respectively. As mentioned above, the second timing signal PIN is outputted from the final terminal of the delay circuit constituting the timing signal generation unit 100. This means that many transistors may exist from the reception of the first timing signal AYP to the generation of the second timing signal PIN, as compared with the number of the first application signal YI, the second application signal BWEN and the third application signal IOSTBP, and thus the largest skew due to the PVT variation occurs in the second timing signal PIN.
A third timing signal Pre_AYP illustrated in FIG. 1 is transmitted from the master chip to the plurality of slave chips Slave, is advanced as compared with the first timing signal AYP, and includes reception timing information of an address signal (not shown) transmitted from the master chip to the plurality of slave chips Slave.